library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity interrupcion is
Port ( --clk : in STD_LOGIC;
vect : in std_LOGIC;
I : out std_logic_vector (11 downto 0));

end interrupcion;
architecture Behavioral of interrupcion is
constant x : std_logic_vector := "ZZZZZZZZZZZZ";
--constant y : std_logic_vector := B"0110"; --esta interrupcion es la del estado 0100
constant y : std_logic_vector := "ZZZZZZZZZZZZ";--esta interrupcion es la del estado 1001
begin
--process (clk,smap)
process(vect)
begin
--if rising_edge (clk) then
			if(vect='1')
				then I <= x;
			elsif (vect='0')
				then I <= y;
			else I <= x;	
			end if;
--		end if;
end process;
end Behavioral;